1. Field of the Invention
The present invention relates to a chip package structure. More particularly, the present invention relates to a chip package structure with superior heat dissipating capacity.
2. Description of the Related Art
In this fast and ever-changing society, information matters to all people. Many types of portable electronic devices are produced which attempts to catch up with our desires to transmit and receive more data. Nowadays, manufacturers have to factor into their chip package many design concepts such as digital architecture, network organization, local area connection and personalized electronic devices. To do so demands special consideration in every aspects of the design process that affects the processing speed, multi-functional capability, integration level, weight and cost of the chip package. In other words, chip packages must be miniaturized and densified. Flip chip (F/C) bonding technique, through the bonding of bumps to a carrier, is currently one of the principle means of reducing overall wiring length over the conventional wire-bonding method. With a shortening of wiring length in a F/C package, signal transmission rate between the chip and a carrier is increased. Thus, F/C packaging technique is one of the most popular methods of forming high-density packages. However, as density of each package continues to increase, heat dissipation becomes a major problem facing chip manufacturers.
FIG. 1 is a schematic cross-sectional view of a conventional chip package with a wire bonding structure. As shown in FIG. 1, the chip packages has a chip 20 with an active surface 22 having a plurality of bonding pads (not shown) thereon. The back of the chip 20 is attached to a carrier 30 so that the active surface 22 faces upwards. The carrier 30 also has a plurality of contact pads (not shown) thereon. A plurality of conductive wires 24 is deployed to connect the various bonding pads with corresponding contact pads so that the chip 20 and the carrier 30 are electrically connected together. Furthermore, an array of solder balls 32 is attached to the carrier 30 on the far side of the chip 20. In other words, the chip package structure 10 has a ball grid array (BGA) packaging structure for connecting electrically with a printed circuit board (PCB) (not shown). In addition, a encapsulating material layer 34 is formed over the carrier 30 to cover the chip 20 and the conductive wires 24. Since the encapsulating material layer 34 is fabricated with material having poor thermal conductivity, the chip package structure 10 has a low heat dissipating capacity.
FIG. 2 is a schematic cross-sectional view of a chip package structure fabricated through a conventional flip-chip packaging technique. As shown in FIG. 2, the chip package structure 40 mainly comprises a chip 50, a carrier 80 and an encapsulating material layer 70. The chip 50 has an active surface 52 with a plurality of bonding pads (not shown) thereon. The carrier 80 also has a plurality of contact pads (not shown) thereon. A plurality of bumps 60 is positioned on the respective bonding pads on the active surface 52 of the chip 50. Furthermore, the bonding pads on the chip 50 and the contact pads on the carrier 80 are electrically connected together through the bumps 60. On the far side of the carrier 80 away from the chip 50, an array of solder balls 90 is attached.
To prevent any damage to the chip 50 due to an incursion of moisture and any damage to the bumps 60 due to mechanical stress, an encapsulating material layer 70 is formed within the bonding gap between the chip 50 and the carrier 80. Conventionally, the encapsulating material layer 70 is formed by channeling a liquid encapsulating material with low viscosity into the bonding gap between the chip 50 and the carrier 80 through capillary effect and then curing the injected material afterwards.
The flip-chip package structure 40 as shown in FIG. 2 has an electrical performance better than the conventional wire-bonded chip package structure 10 in FIG. 1. Furthermore, the flip-chip package structure 40 has an ultra-thin thickness suitable for embedding inside a slim device. However, it takes considerable time to fill up the bonding gap between the chip 50 and the carrier 80 with liquid encapsulating material through capillary effect alone. Hence, this method is unsuitable for economic mass production. Moreover, the number of bumps 60 within the bonding gap, the distribution of the bumps 60 within the package as well as the distance of separation between the flip chip 50 and the carrier 80 are some of the major factors affecting the capillary flow of liquid encapsulating material. Because the capillary effect is utilized to draw liquid encapsulating material into the space between the chip 50 and the carrier 80, any variation of the liquid flow conditions is likely to hinder the filling process leading to the possible formation of voids. In other words, reliability of the package will be adversely affected.
In addition, the chip 50 within the chip package structure 40 is directly exposed. Hence, the chip 50 could be damaged when markings are imprinted on the surface of the chip 50 or the chip package structure 40 is picked up using a suction pad gripping the back of the chip 50. To avoid these defects, an alternative chip package structure is provided. FIGS. 3A and 3B are cross-sectional views of alternative chip package structures fabricated through another conventional flip-chip packaging technique. As shown in FIG. 3A, an additional over mold layer 72 is formed over the chip package structure 40 in FIG. 2 to protect the chip 50 against possible damage.
However, the need to form an additional over mold layer 72 increases the overall processing time resulting a drop in productivity. Moreover, delamination is a likely occurrence at the interface between the encapsulating material layer 70 and the over mold layer 72. In other words, overall reliability of the chip package structure 42 will drop.
To avoid delamination and increase productivity, an improved chip package structure 44 disclosed in Japanese pattern J392698 is shown in FIG. 3B. As shown in FIG. 3B, a simultaneous molding operation is carried out to form an encapsulating material layer 74 that covers the chip 50 and the carrier 80 and fills the bonding gap between the chip 50 and the carrier 80. Although the simultaneous molding process is able to prevent delamination, the encapsulating material layer 74 covering the chip still leads to poor heat dissipation from the chip package structure 44.